This disclosure relates to fabrication of features in a semiconductor device, including fabrication via etching and deposition processes.
Fabrication of semiconductor devices is a multi-step process of forming features on a semiconductor substrate or other substrate. Steps can include material growth, patterning, doping, deposition, etching, metallization, planarization, and so forth. Features formed on a substrate can include various transistors. Transistors can be planar or non-planar, and can also have single gates or multiple gates. Non-planar transistors (sometimes referred to as 3D transistors) include the FinFET (fin field effect transistor), among others. Such non-planar transistors typically include a vertically-oriented or raised fin that functions as a channel between the source and drain. The gate is also vertically-oriented or raised and is positioned over the fin (on top of the fin and around fin sidewalls). Such non-planar transistors can have multiple fins and/or multiple gates. Planar transistors also have associated heights, though relative heights of non-planar features are usually greater than those of planar transistors.
Fabrication of semiconductor devices often includes deposition of spacer and/or dummy materials to assist in constructing a given feature design, including features on non-planar transistors. Sidewall spacers are often specified on non-planar transistors for improved gate functionality. As the dimensions of the transistor gate continue to shrink, the fringe capacitance between the gate and contact, as well as between the gate and facet of the source/drain (S/D), has increased. To counter this increase in fringe capacitance, low-k dielectric materials have been implemented as the spacer material. The success of a spacer is affected by a spacer etch process, which can affect both the dielectric constant of the spacer, as well as spacer coverage.